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Disambiguation of "Yamashita, Shigeru"

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A systematic methodology for design and analysis of approximate array multipliers.

, , , , and . APCCAS, page 352-354. IEEE, (2016)

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Shigeru Noda

Shigeru Taguchi

Kiyonobu Yamashita

Miki Yamashita

Aiko Yamashita

 

Other publications of authors with the same name

Reconfigurable 1-Bit Processor Array with Reduced Wirng Area., , , and . ERSA, page 225-234. CSREA Press, (2005)A systematic methodology for design and analysis of approximate array multipliers., , , , and . APCCAS, page 352-354. IEEE, (2016)Changing the Gate Order for Optimal LNN Conversion., and . RC, volume 7165 of Lecture Notes in Computer Science, page 89-101. Springer, (2011)Reducing the Overhead of Mapping Quantum Circuits to IBM Q System., , and . ISCAS, page 1-5. IEEE, (2019)Quantum Sampling for Balanced Allocations., , and . COCOON, volume 2697 of Lecture Notes in Computer Science, page 304-318. Springer, (2003)A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips., , and . ASP-DAC, page 225-230. IEEE, (2014)Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles., , , and . IEICE Trans. Inf. Syst., 90-D (2): 395-402 (2007)Multi-Party Quantum Communication Complexity with Routed Messages., , and . IEICE Trans. Inf. Syst., 92-D (2): 191-199 (2009)Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays., , , , , , , and . DATE, page 1335-1338. IEEE, (2020)On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design., and . PRDC, page 118-119. IEEE Computer Society, (2013)