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Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism.

, , , , , and . Int. J. Comput. Their Appl., 14 (2): 79-91 (2007)

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Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance., and . PRDC, page 23-24. IEEE, (2019)A low-power high-speed accuracy-controllable approximate multiplier design., , and . ASP-DAC, page 605-610. IEEE, (2018)Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation., and . CAINE, page 282-287. ISCA, (2003)Profiling with Helper Threads., and . Parallel and Distributed Computing and Networks, page 1-6. IASTED/ACTA Press, (2005)Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture., and . ISICT, volume 90 of ACM International Conference Proceeding Series, page 190-195. Trinity College Dublin, (2004)Signal probability control for relieving NBTI in SRAM cells., , and . ISQED, page 660-666. IEEE, (2010)Dynamically reducing overestimated design margin of MultiCores., , and . HPCS, page 403-409. IEEE, (2012)Table size reduction for data value predictors by exploiting narrow width values., and . ICS, page 196-205. ACM, (2000)Folding Active List for High Performance and Low Power., and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 33-42. Springer, (2005)Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction., and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 530-539. Springer, (2003)