( en | de | ru )

 

Disambiguation of "Ha, Yajun"

Author of the publication

copydeleteadd this publication to your clipboard
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters.

, and . ARC, volume 7199 of Lecture Notes in Computer Science, page 174-186. Springer, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yajun Fang

Yajun Xiao

Yajun Cheng

Hoang Ha

Ngo Ha

 

Other publications of authors with the same name

Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects., , and . LASCAS, page 1-4. IEEE, (2020)ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning., , and . FPL, page 1-11. IEEE, (2016)Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects., , , , and . PDPTA, CSREA Press, (2000)Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)., and . FPGA, page 268. ACM, (2012)Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (12): 3503-3507 (2021)HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4295-4308 (November 2023)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications., , , , , , , , , and 2 other author(s). CoRR, (2023)An energy-efficient system on a programmable chip platform for cloud applications., , , , , , and . J. Syst. Archit., (2017)Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools., , , and . FPL, page 279-284. IEEE, (2007)