( en | de | ru )

 

Disambiguation of "Jégo, Christophe"

Author of the publication

copydeleteadd this publication to your clipboard
Software polar decoder on an embedded processor.

, , and . SiPS, page 180-185. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mathieu Jégou

Cyrille Jégourel

Roland Jégou

Arnaud Jégou

Nicolas Jégou

 

Other publications of authors with the same name

Efficient architecture for Reed Solomon block turbo code., , , , and . ISCAS, IEEE, (2006)Reed-Solomon behavioral virtual component for communication systems., , , , and . ISCAS (4), page 173-176. IEEE, (2004)FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems.. ERSA, page 9-18. CSREA Press, (2009)A highly parallel Turbo Product Code decoder without interleaving resource., , , , and . SiPS, page 1-6. IEEE, (2008)Comparison of different schedulings for the ADMM based LDPC decoding., , , , and . ISTC, page 51-55. IEEE, (2016)Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis., , , and . ICECS, page 661-664. IEEE, (2018)Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes., , , , and . SoftCOM, page 1-5. IEEE, (2017)Evaluation of the hardware complexity of the ADMM approach for LDPC decoding., , , , and . WCNC, page 1-6. IEEE, (2016)Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis., , , and . SiPS, page 242-247. IEEE, (2019)Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy., and . DASIP, page 8. IEEE, (2013)