( en | de | ru )

 

Disambiguation of "Nandwana, Romesh Kumar"

Author of the publication

copydeleteadd this publication to your clipboard
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.

, , , , , , , and . CICC, page 1-4. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Romesh Sharma

Romesh Chandra Sen

Rohini Kumar

Pardeep Kumar

Aditya Kumar

 

Other publications of authors with the same name

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS., , , , and . ISSCC, page 1-3. IEEE, (2015)8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS., , , , and . ISSCC, page 152-153. IEEE, (2017)Clock multiplication techniques for high-speed I/Os. University of Illinois Urbana-Champaign, USA, (2017)A 7 pA/$\surdHz$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS., , , , , , and . ISSCC, page 206-207. IEEE, (2023)A 0.7V time-based inductor for fully integrated low bandwidth filter applications., , , , , , and . CICC, page 1-4. IEEE, (2017)A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)High-Performance CMOS TIA for Data Center Optical Interconnects., , , , , , and . BCICTS, page 9-16. IEEE, (2022)A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2306-2320 (2017)A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler., , , , and . IEEE J. Solid State Circuits, 54 (7): 2049-2058 (2019)