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Disambiguation of "Sehgal, Naresh"

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A novel technique for sea of gates global routing.

, , and . ACM Great Lakes Symposium on VLSI, page 71-74. ACM, (2000)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

A novel ultra-fast heuristic for VLSI CAD steiner trees., , and . ACM Great Lakes Symposium on VLSI, page 192-197. ACM, (2003)Timing Driven Placement using Physical Net Constraints., , and . DAC, page 780-783. ACM, (2001)A sensitivity based placer for standard cells., , and . ACM Great Lakes Symposium on VLSI, page 193-196. ACM, (2000)A novel technique for sea of gates global routing., , and . ACM Great Lakes Symposium on VLSI, page 71-74. ACM, (2000)A gridless multi-layer area router., , and . Great Lakes Symposium on VLSI, page 158-161. IEEE, (1994)GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs., , , , , , and . VLSI Design, page 448-452. IEEE Computer Society, (1999)Detailed Placement with Net Length Constraints., , and . IWSOC, page 22-27. IEEE Computer Society, (2003)An object-oriented cell library manager., , and . ICCAD, page 750-753. IEEE Computer Society / ACM, (1994)Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations., , and . VLSI Design, page 53-58. IEEE Computer Society, (1998)A general approach for regularity extraction in datapath circuits., , , , and . ICCAD, page 332-339. ACM / IEEE Computer Society, (1998)