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Feature extraction by uniform structure threshold logic networks.

, and . ICASSP, page 1445-1448. IEEE, (1986)

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Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction., , , , , and . ARC, volume 6578 of Lecture Notes in Computer Science, page 230-241. Springer, (2011)ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension., and . ISLPED, page 1-6. ACM, (2024)Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping., , , , , , , and . FPT, page 349-352. IEEE, (2010)Cool Mega-Array: A highly energy efficient reconfigurable accelerator., , , , , , , , , and . FPT, page 1-8. IEEE, (2011)Feature extraction by uniform structure threshold logic networks., and . ICASSP, page 1445-1448. IEEE, (1986)Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations., , and . FPT, page 1-8. IEEE, (2011)A vertical bubble flow network using inductive-coupling for 3-D CMPs., , , , , , , , and . NOCS, page 49-56. ACM/IEEE Computer Society, (2011)A fast processor for 3-d device simulation using systolic arrays., , and . Syst. Comput. Jpn., 22 (1): 39-48 (1991)Accent phrase segmentation using pitch pattern clustering., and . ICASSP, page 217-220. IEEE Computer Society, (1992)MuCCRA-3: a low power dynamically reconfigurable processor array., , , , , , and . ASP-DAC, page 377-378. IEEE, (2010)