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Disambiguation of "Endoh, Tetsuo"

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A compact and low power logic design for multi-pillar vertical MOSFETs.

, and . ISCAS, page 309-312. IEEE, (2010)

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Tetsuo Morino

Tetsuo Kishimoto

 

Other publications of authors with the same name

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing., , , , , , , , and . Proc. IEEE, 104 (10): 1844-1863 (2016)A compact and low power logic design for multi-pillar vertical MOSFETs., and . ISCAS, page 309-312. IEEE, (2010)0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation., , , , , , , , and . IEEE J. Solid State Circuits, 36 (6): 988-996 (2001)Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system., , , , and . NVMTS, page 1-5. IEEE, (2018)Nonvolatile logic and memory devices based on spintronics.. ISCAS, page 13-16. IEEE, (2015)Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3., , and . Neural Comput. Appl., 35 (15): 11013-11041 (May 2023)A novel memory test system with an electromagnet for STT-MRAM testing., , , , , , and . NVMTS, page 1-4. IEEE, (2019)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET., and . IEICE Trans. Electron., 94-C (5): 737-742 (2011)Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application., , and . IEEE Access, (2020)