( en | de | ru )

 

Disambiguation of "Alioto, Massimo"

Author of the publication

copydeleteadd this publication to your clipboard
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Massimo Malagó

Massimo Viola

Massimo Tallarida

Massimo Busin

Massimo Moser

 

Other publications of authors with the same name

Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS., , , and . ISSCC, page 482-484. IEEE, (2012)Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V., , and . ISCAS, page 1-5. IEEE, (2018)Efficient and Accurate Models of Output Transition Time in CMOS Logic., , and . ICECS, page 1264-1267. IEEE, (2007)Analysis of the impact of random process variations in CMOS tapered buffers., , and . ICECS, page 57-60. IEEE, (2009)Energy evaluation in RLC tree circuits with exponential input., , and . ICECS, page 578-581. IEEE, (2008)Analysis of the impact of process variations on static logic circuits versus fan-in., , and . ICECS, page 137-140. IEEE, (2008)Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders., and . ICECS, page 518-521. IEEE, (2006)A closed-form energy model for VLSI circuits under wide voltage scaling., and . ICECS, page 548-551. IEEE, (2016)Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations., , , , and . ISCAS, page 2043-2046. IEEE, (2011)Analysis of layout density in FinFET standard cells and impact of fin technology.. ISCAS, page 3204-3207. IEEE, (2010)