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A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

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Design of a sub-1-V nanopower CMOS current reference., , , and . ECCTD, page 1-4. IEEE, (2017)Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory., , , and . ICECS, page 123-124. IEEE, (2019)An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops., , , and . ICECS, page 158-161. IEEE, (2019)A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A Framework for Energy-Efficiency in Smart Home Environments., , , , and . PRO-VE, volume 434 of IFIP Advances in Information and Communication Technology, page 237-244. Springer, (2014)Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers., , , and . ASICON, page 1-4. IEEE, (2019)A portable class of 3-transistor current references with low-power sub-0.5 V operation., , , , , and . Int. J. Circuit Theory Appl., 46 (4): 779-795 (2018)Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework., , , , , and . SMACD, page 1-4. IEEE, (2017)Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs., , , , , , and . SMACD, page 85-88. IEEE, (2019)Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations., , , , , and . RTSI, page 1-4. IEEE, (2018)