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High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms.

, , , , , and . FCCM, page 37-44. IEEE Computer Society, (2018)

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LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (4): 564-577 (2010)Buffer block planning for interconnect planning and prediction., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 929-937 (2001)Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs., , , , , , , and . DAC, page 29:1-29:6. ACM, (2017)Automated accelerator generation and optimization with composable, parallel and pipeline architecture., , , and . DAC, page 154:1-154:6. ACM, (2018)Pin assignment with global routing for general cell designs.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (11): 1401-1412 (1991)HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support., , and . CODES+ISSS, page 295-304. ACM, (2011)Delay optimal low-power circuit clustering for FPGAs with dual supply voltages., and . ISLPED, page 70-73. ACM, (2004)Locality and Utilization in Placement Suboptimality., , , , and . Modern Circuit Placement, Springer, (2007)A Two-pole Circuit Model for VLSI High-speed Interconnection., , , , and . ISCAS, page 2129-2132. IEEE, (1993)A unified optimization framework for simultaneous gate sizing and placement under density constraints., , and . ISCAS, page 1207-1210. IEEE, (2011)