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A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.

S. Okumura, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto. ASP-DAC, page 79-80. IEEE, (2013)

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Shunsuke Saito

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Bit error rate estimation in SRAM considering temperature fluctuation.Y. Kagiyama, S. Okumura, K. Yanagida, S. Yoshimoto, Y. Nakata, S. Izumi, H. Kawaguchi, and M. Yoshimoto. ISQED, page 516-519. IEEE, (2012)0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.Y. Nakata, S. Okumura, H. Kawaguchi, and M. Yoshimoto. ISLPED, page 219-224. ACM, (2010)7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory.S. Okumura, Y. Kagiyama, Y. Nakata, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2693-2700 (2011)A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 91-C (4): 543-552 (2008)A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). ISQED, page 16-23. IEEE, (2014)0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM.H. Noguchi, S. Okumura, T. Takagi, K. Kugata, M. Yoshimoto, and H. Kawaguchi. ISQED, page 219-222. IEEE, (2011)Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores.K. Kugata, S. Soda, Y. Nakata, S. Okumura, S. Izumi, M. Yoshimoto, and H. Kawaguchi. ARCS Workshops, volume P-200 of LNI, page 375-384. GI, (2012)Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy.S. Okumura, Y. Nakata, K. Yanagida, Y. Kagiyama, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2011)A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19.S. Okumura, S. Yoshimoto, H. Kawaguchi, and M. Yoshimoto. ESSCIRC, page 527-530. IEEE, (2011)A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, and M. Yoshimoto. ASP-DAC, page 77-78. IEEE, (2013)

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Disambiguation of "Okumura, Shunsuke"

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A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.

Please choose a person to relate this publication to

Shunsuke Saito

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Okumura, Shunsuke"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.

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Shunsuke Saito

Other publications of authors with the same name

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A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.