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Cache Coherence Protocol Design for Active Memory Systems., , and . PDPTA, page 83-89. CSREA Press, (2002)Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions.. ISCA, page 71-84. IEEE, (2021)Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.. MICRO, page 401-412. ACM, (2009)Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors., and . ICPP, page 4. IEEE Computer Society, (2007)Performance Evaluation of Concurrent Lock-free Data Structures on GPUs., and . ICPADS, page 53-60. IEEE Computer Society, (2012)Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors., and . ICS, page 3:1-3:14. ACM, (2016)Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources., , , and . HPCA, page 13-24. IEEE Computer Society, (2017)Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems., and . ICCD, page 557-564. IEEE Computer Society, (2015)Bypass and insertion algorithms for exclusive last-level caches., , and . ISCA, page 81-92. ACM, (2011)Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors., and . IPDPS Workshops, page 18-29. IEEE Computer Society, (2017)