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Другие публикации лиц с тем же именем

Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions.. ISCA, стр. 71-84. IEEE, (2021)Cache Coherence Protocol Design for Active Memory Systems., , и . PDPTA, стр. 83-89. CSREA Press, (2002)Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors., и . ICPP, стр. 4. IEEE Computer Society, (2007)Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors., и . ICS, стр. 3:1-3:14. ACM, (2016)Performance Evaluation of Concurrent Lock-free Data Structures on GPUs., и . ICPADS, стр. 53-60. IEEE Computer Society, (2012)Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.. MICRO, стр. 401-412. ACM, (2009)PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.. HPCA, стр. 227-238. IEEE Computer Society, (2009)Scavenger: A New Last Level Cache Architecture with Global Block Priority., , , , и . MICRO, стр. 421-432. IEEE Computer Society, (2007)Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches., , , , и . PACT, стр. 293-304. ACM, (2012)SMTp: An Architecture for Next-generation Scalable Multi-threading., и . ISCA, стр. 124-137. IEEE Computer Society, (2004)