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YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.

Y. Chen, G. Yin, Z. Tan, M. Lee, Z. Yang, Y. Liu, H. Yang, K. Ma, and X. Li. DAC, page 1093-1098. ACM, (2022)

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Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental programB. Lee. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensorsM. Lee. HU Berlin, (2009)

Hyemin Lee

Clara Lee

Other publications of authors with the same name

GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph.Y. Chen, G. Dai, M. Zhou, M. Lee, N. Challapalle, G. Yin, Z. Yang, Y. Liu, H. Yang, V. Narayanan and 1 other author(s). CoRR, (2022)FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.M. Lee, W. Tang, B. Xue, J. Wu, M. Ma, Y. Wang, Y. Liu, D. Fan, V. Narayanan, H. Yang and 1 other author(s). ISLPED, page 127-132. ACM, (2020)SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree.Y. Chen, G. Yin, M. Zhou, W. Tang, Z. Yang, M. Lee, X. Du, J. Yue, J. Liu, H. Yang and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2762-2773 (July 2023)Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM.M. Lee, W. Tang, Y. Chen, J. Wu, H. Zhong, Y. Xu, Y. Liu, H. Yang, V. Narayanan, and X. Li. DAC, page 1-6. IEEE, (2023)ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns.Y. Chen, G. Yin, H. Zhong, M. Lee, H. Yang, S. George, V. Narayanan, and X. Li. ASPDAC, page 153-158. IEEE, (2024)A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM.G. Yin, Y. Chen, M. Lee, X. Du, Y. Ke, W. Tang, Z. Chen, M. Zhou, J. Yue, H. Yang and 3 other author(s). CICC, page 1-2. IEEE, (2024)YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.Y. Chen, G. Yin, Z. Tan, M. Lee, Z. Yang, Y. Liu, H. Yang, K. Ma, and X. Li. DAC, page 1093-1098. ACM, (2022)Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability.Y. Chen, G. Yin, M. Lee, W. Tang, Z. Yang, Y. Liu, H. Yang, and X. Li. ICCAD, page 45:1-45:9. ACM, (2022)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.Y. Chen, M. Lee, G. Dai, M. Zhou, N. Challapalle, T. Wang, Y. Yu, Y. Liu, Y. Wang, H. Yang and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)

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Disambiguation of "Lee, Mingyen"

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YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.

Please choose a person to relate this publication to

Xavier Lee Lee

Bongsoo Lee

Min-Hi Lee

Hyemin Lee

Clara Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Mingyen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.

Please choose a person to relate this publication to

Xavier Lee Lee

Bongsoo Lee

Min-Hi Lee

Hyemin Lee

Clara Lee

Other publications of authors with the same name

Disambiguation

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YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip.