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Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM.

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GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph., , , , , , , , , and 1 other author(s). CoRR, (2022)FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface., , , , , , , , , and 1 other author(s). ISLPED, page 127-132. ACM, (2020)SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree., , , , , , , , , and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2762-2773 (July 2023)Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM., , , , , , , , , and . DAC, page 1-6. IEEE, (2023)ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns., , , , , , , and . ASPDAC, page 153-158. IEEE, (2024)A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM., , , , , , , , , and 3 other author(s). CICC, page 1-2. IEEE, (2024)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility., , , , , , , , , and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability., , , , , , , and . ICCAD, page 45:1-45:9. ACM, (2022)YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip., , , , , , , , and . DAC, page 1093-1098. ACM, (2022)