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Disambiguation of "Michail, Harris E."

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Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor.

, , , and . ICECS, page 243-246. IEEE, (2010)

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Melvin Harris

Kathleen Harris

Nigel Harris

Horton Harris

Martin Harris

 

Other publications of authors with the same name

High-performance FPGA implementations of the cryptographic hash function JH., , , and . IET Comput. Digit. Tech., 7 (1): 29-40 (2013)Throughput Optimization of the Cipher Message Authentication Code., , , and . DSP, page 495-498. IEEE, (2007)High performance pipelined FPGA implementation of the SHA-3 hash algorithm., , and . MECO, page 68-71. IEEE, (2015)Evolution of the e-Museum Concept through Exploitation of Cryptographic Algorithms., , , and . EuroMed, volume 7616 of Lecture Notes in Computer Science, page 291-300. Springer, (2012)High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach., , , , , and . SECRYPT, page 126-135. SciTePress, (2012)Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis., , and . CS2@HiPEAC, page 13-18. ACM, (2015)Server side hashing core exceeding 3 Gbps of throughput., , , , and . Int. J. Secur. Networks, 2 (3/4): 228-238 (2007)Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function., , , and . ICECS, page 567-570. IEEE, (2004)VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption., , , and . ICECS, page 1-4. IEEE, (2005)Cipher Block Based Authentication Module: a Hardware Design Perspective., , , , and . J. Circuits Syst. Comput., 20 (2): 163-184 (2011)