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Disambiguation of "Wu, An-Yeu"

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A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system.

, , , and . ESSCIRC, page 534-537. IEEE, (2010)

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Changseon Yeum

Danny Yeung

Thomas Yeung

Maureen W Yeung

Kam Yeung

 

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New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform., , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (8): 532-536 (2013)A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification., , and . ISCAS, page 1-5. IEEE, (2021)Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem., and . ISCAS, page 357-360. IEEE, (2000)A memory-reduced log-MAP kernel for turbo decoder., , and . ISCAS (2), page 1032-1035. IEEE, (2005)On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems., , , and . SiPS, page 422-427. IEEE, (2006)Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism., , , and . CoRR, (2018)VLSI design of dual-mode Viterbi/turbo decoder for 3GPP., , , and . ISCAS (2), page 773-776. IEEE, (2004)Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules., , , and . ISCAS, page 869-872. IEEE, (2007)A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM., , , and . ISCAS, page 2445-2448. IEEE, (2009)Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems., , , , and . VLSI-DAT, page 1-4. IEEE, (2012)