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Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems., , and . DATE, page 1-6. European Design and Automation Association, (2014)BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC., , , , and . ICCD, page 78-85. IEEE, (2023)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , and 18 other author(s). DATE, page 1-6. IEEE, (2023)The Hardware Foundation of 6G: The NEW-6G Approach., , , , , , , , , and 1 other author(s). EuCNC, page 423-428. IEEE, (2022)Hardware-aware training of models with synaptic delays for digital event-driven neuromorphic processors., , , , , , , , and . CoRR, (2024)Digital Predistortion with Compressed Observations for Cloud-Based Learning., , , , , and . SiPS, page 40-45. IEEE, (2021)Architecture and optimal configuration of a real-time multi-channel memory controller., , and . DATE, page 1307-1312. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards ASIP Architecture-Driven Algorithm Development., , and . IESS, volume 576 of IFIP Advances in Information and Communication Technology, page 91-100. Springer, (2019)Quater-imaginary base for complex number arithmetic circuits., and . DATE, page 1481-1483. IEEE, (2018)Dependability of Future Edge-AI Processors: Pandora's Box., , , , , , , , , and 3 other author(s). ETS, page 1-6. IEEE, (2023)