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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties., , , and . IEEE Des. Test, 36 (2): 81-87 (2019)Application specific processor for multi-standard video decoding., and . ISOCC, page 436-439. IEEE, (2011)New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding., , and . IEEE Trans. Circuits Syst. Video Techn., 20 (7): 1007-1017 (2010)Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier., and . FPGA, page 249. ACM, (2004)Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU., , , , , , and . ISLPED, page 1-6. IEEE, (2023)Comparison between STDP and Gradient-descent Training Processes for Spiking Neural Networks Using MNIST Digits., , , and . ICTC, page 1732-1734. IEEE, (2022)Design of a Reversible PLD Architecture., , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 85-90. Springer, (2007)How to Link SNOMED CT Procedure and WHO International Classification of Health Interventions (ICHI)., , , , and . eHealth, volume 236 of Studies in Health Technology and Informatics, page 40-47. IOS Press, (2017)A Logarithmic Domain Algorithm of the Hodgkin-Huxley Neuron Model for Hardware Implementations., , and . ICEIC, page 1-3. IEEE, (2022)The VDSL Deployments and Their Associated Crosstalk with xDSL Systems., , and . ICT, volume 3124 of Lecture Notes in Computer Science, page 1296-1302. Springer, (2004)