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GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.

, , , , , , and . FPGA, page 143-153. ACM, (2024)

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FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs., , , , and . FPGA, page 15-25. ACM, (2023)MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network., , , , , , , , and . ICCAD, page 1-9. IEEE, (2023)Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis., , , and . DATE, page 1130-1135. IEEE, (2019)PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN., , , and . DAC, page 1-6. IEEE, (2023)Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis., , , , and . ICCAD, page 1-6. ACM, (2019)A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms., , , , and . FPGA, page 188. ACM, (2019)AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (9): 2769-2782 (September 2024)GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network., , , , , , and . FPGA, page 143-153. ACM, (2024)LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms., , , , and . DAC, page 1. ACM, (2019)FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications., , , , , , and . FPL, page 269-276. IEEE, (2020)