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A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero.

H. Shin, J. Kim, D. Jang, D. Cho, Y. Jung, H. Cho, U. Lee, C. Kim, S. Ha, and M. Je. VLSI Circuits, page 1-2. IEEE, (2020)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Eva Jüngel

Präklinische Studien zur Behandlung des Nierenzellkarzinoms durch den Histondeacetylase-Inhibitor Valproat und Interferon-alphaE. Jüngel. Uni Frankfurt Main, (2009)

Yvonne Jung

Sarah Jung

Irina Jung

Nina Jung

Other publications of authors with the same name

A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation.D. Cho, H. Cho, S. Oh, Y. Jung, S. Ha, C. Kim, and M. Je. CICC, page 1-2. IEEE, (2022)An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording.W. Lee, Y. Jung, H. Jeon, J. Koo, S. Oh, S. Kweon, and M. Je. ISCAS, page 1-5. IEEE, (2024)A High-throughput Impedance Measurement IC with Baseline-Canceling Peak Detector.A. Malik, S. Kweon, K. Ellahi, M. Akram, S. Cheon, Y. Jung, M. Je, H. Cheema, and S. Ha. ISCAS, page 1-5. IEEE, (2024)A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface.H. Jeon, J. Bang, Y. Jung, I. Choi, and M. Je. IEEE J. Solid State Circuits, 54 (10): 2658-2670 (2019)A 187dB FoMS 46fJ/Conv 2nd-order Highpass Δ∑ Capacitance-to-Digital Converter.Y. Jung, S. Oh, J. Koo, S. Park, J. Suh, D. Cho, S. Ha, and M. Je. VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter.Y. Jung, J. Koo, S. Oh, S. Park, J. Suh, D. Cho, and M. Je. CICC, page 1-2. IEEE, (2023)An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.S. Kweon, J. Gil, C. Park, S. Oh, Y. Jung, I. Choi, S. Cheon, H. Dang, J. Koo, G. Kim and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Dynamic-Range-Enhancement Techniques for Artifact-Tolerant Biopotential-Acquisition ICs.Y. Jung, S. Kweon, T. Lee, K. Jeong, S. Ha, and M. Je. IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3090-3095 (2022)A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers.S. Oh, S. Park, Y. Jung, J. Koo, D. Cho, S. Ha, and M. Je. VLSI Technology and Circuits, page 1-2. IEEE, (2023)A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC.Y. Jung, S. Kweon, H. Jeon, J. Lee, Y. Kim, S. Oh, J. Koo, and M. Je. ISCAS, page 1-4. IEEE, (2023)

BibSonomy

Disambiguation of "Jung, Yoontae"

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URL
DOI
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A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero.

Please choose a person to relate this publication to

Eva Jüngel

Yvonne Jung

Sarah Jung

Irina Jung

Nina Jung

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jung, Yoontae"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero.

Please choose a person to relate this publication to

Eva Jüngel

Yvonne Jung

Sarah Jung

Irina Jung

Nina Jung

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero.