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DVFS in loop accelerators using BLADES., , , , и . DAC, стр. 894-897. ACM, (2008)Bridging the computation gap between programmable processors and hardwired accelerators., , , и . HPCA, стр. 313-322. IEEE Computer Society, (2009)CoreGenesis: erasing core boundaries for robust and configurable performance., , , , и . PACT, стр. 571-572. ACM, (2010)A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation., , , и . CICC, стр. 1-4. IEEE, (2013)PEPSC: A Power-Efficient Processor for Scientific Computing., , , и . PACT, стр. 101-110. IEEE Computer Society, (2011)A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning., , , , , , , , и . IISWC, стр. 87-100. IEEE, (2021)Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache., , , , , , и . CGO, стр. 179-190. IEEE Computer Society, (2005)Power-efficient medical image processing using PUMA., , и . SASP, стр. 29-34. IEEE Computer Society, (2009)Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism., , , , , и . ISCA, стр. 548-560. ACM, (2017)Increasing the number of effective registers in a low-power processor using a windowed register file., , , , , , и . CASES, стр. 125-136. ACM, (2003)