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You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference., , and . ACM Trans. Reconfigurable Technol. Syst., 11 (3): 20:1-20:23 (2018)Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation., and . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 31:1-31:24 (June 2023)Are FPGAs suffering from the innovator's dilemna?, and . FPGA, page 135-136. ACM, (2013)Timing-driven placement for FPGAs., , and . FPGA, page 203-213. ACM, (2000)Automatic generation of FPGA routing architectures from high-level descriptions., and . FPGA, page 175-184. ACM, (2000)A Fast Routability-Driven Router for FPGAs., , and . FPGA, page 140-149. ACM, (1998)HPIPE NX: Boosting CNN Inference Acceleration Performance with AI-Optimized FPGAs., , , and . FPT, page 1-9. IEEE, (2022)cuSCNN : an Efficient CUDA Implementation of Sparse CNNs., , , , and . HEART, page 107-113. ACM, (2023)From TensorFlow Graphs to LUTs and Wires: Automated Sparse and Physically Aware CNN Hardware Generation., and . FPT, page 56-65. IEEE, (2020)Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs., , , , , , , and . FPT, page 10-19. IEEE, (2020)