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Disambiguation of "Beyne, Eric"

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Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).

, , , , , , and . SLIP, page 17-23. IEEE, (2021)

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Emmanuelle Beyne

Dimitry Beynenson

Friederike Erichsen-Wendt

Claus Erichsen

Kay Erichsen

 

Other publications of authors with the same name

Design of Test Modules for the Analysis of MCM Interconnects., , and . ED&TC, page 614. IEEE Computer Society, (1996)Design issues in heterogeneous 3D/2.5D integration., , , , , and . ASP-DAC, page 403-410. IEEE, (2013)Impact of 3D design choices on manufacturing cost., , , , and . 3DIC, page 1-5. IEEE, (2009)A novel concept for ultra-low capacitance via-last TSV., , , , , and . 3DIC, page 1-4. IEEE, (2010)In-tier diagnosis of power domains in 3D TSV ICs., , , , , , , , , and 1 other author(s). 3DIC, page 1-6. IEEE, (2011)Constant Impedance Scaling Paradigm for Scaling LC transmission lines., , , , , , and . ISQED, page 387-392. IEEE Computer Society, (2006)Active-lite interposer for 2.5 & 3D integration., , , , , , , , , and 5 other author(s). VLSIC, page 222-. IEEE, (2015)Thermal experimental and modeling analysis of high power 3D packages., , , , , and . ICICDT, page 1-4. IEEE, (2015)System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform., , , , , , and . IEEE Embed. Syst. Lett., 6 (4): 85-88 (2014)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects., , , , , , , , , and 1 other author(s). Microelectron. Reliab., (2017)