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Disambiguation of "Hulina, Paul T."

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Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module.

, , and . ISCA, page 236-245. ACM, (1992)

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T Peters

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Other publications of authors with the same name

On Tracey's Internal State Assignment Method., and . IEEE Trans. Computers, 19 (5): 458 (1970)Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits, and . SWAT, page 104-108. IEEE Computer Society, (1970)Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories., , , and . ICPP (1), page 212-219. CRC Press, (1994)An electronics manufacturing minor in engineering with emphasis on rapid prototyping., and . MSE, page 21-22. IEEE Computer Society, (1997)Classification and Performance Evaluation of Instruction Buffering Techniques., , , and . ISCA, page 150-159. ACM, (1991)Program Balance and Its Impact on High Performance RISC Architectures., , , and . HPCA, page 370-379. IEEE Computer Society, (1995)Structured Data Access Mechanisms for a Decoupled Computer Architecture., , and . ICPP (2), page 285-289. CRC Press, (1994)Design and VLSI implementation of an access processor for a decoupled architecture., , , and . Microprocess. Microsystems, 16 (5): 237-247 (1992)Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits, and . Inf. Control., 20 (2): 114-124 (March 1972)A WWW facilitated rapid system prototyping class., and . MSE, page 99-100. IEEE Computer Society, (1997)