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Functional test environment for time-triggered control systems in complex MPSoCs.

, , , , and . Microprocess. Microsystems, (2020)

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A Hypervisor Architecture for Low-Power Real-Time Embedded Systems., , , , , , and . DSD, page 252-259. IEEE Computer Society, (2018)Functional test environment for time-triggered control systems in complex MPSoCs., , , , and . Microprocess. Microsystems, (2020)SAFEPOWER: Application of Power Management Techniques in SoCs for Safety-Relevant Systems., , , , and . COINS, page 104-109. ACM, (2019)A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs., and . COINS, page 86-91. ACM, (2019)Experimental Evaluation of Scenario Aware Synchronous Data Flow based Power Management., , , , and . COINS, page 80-85. ACM, (2019)SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems., , , , , , , , , and 8 other author(s). Microprocess. Microsystems, (2017)Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory Communication., , , , and . DATE, page 1715-1720. IEEE, (2019)Capturing Neural-Networks as Synchronous Dataflow Graphs., , and . MBMV, page 1-10. VDE / IEEE, (2020)Towards power management verification of time-triggered systems using virtual platforms., , , , and . SAMOS, page 81-88. ACM, (2018)