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Disambiguation of "Vernalde, Serge"

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ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.

, , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 61-70. Springer, (2003)

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Elena Sergeyev

Nikolai Sergeev

Tatiana Sergey

Dieter Sergel

Jean-Frédéric Sergejew

 

Other publications of authors with the same name

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays., , , and . FPT, page 33-40. IEEE, (2004)Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications., , , , , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1135-1138. Springer, (2002)A SW/HW Interface API for Java/FPGA Co-Designed Applets., , , , , and . FCCM, page 269-270. IEEE Computer Society, (2001)Operating-system controlled network on chip., , , , and . DAC, page 256-259. ACM, (2004)Virtual Java/FPGA interface for networked reconfiguration., , , , , , and . ASP-DAC, page 558-563. ACM, (2001)Low Power Digital Frequency Conversion Architectures., , , and . J. VLSI Signal Process., 18 (2): 187-197 (1998)Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study., , , and . DATE, page 1224-1229. IEEE Computer Society, (2004)A Hardware Virtual Machine for the Networked Reconfiguration., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 194-199. IEEE Computer Society, (2000)A Technique for Combined Virtual Prototyping and Hardware Design., , , , , and . International Workshop on Rapid System Prototyping, page 156-161. IEEE Computer Society, (1998)A new algorithm for elimination of common subexpressions., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (1): 58-68 (1999)