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1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.

T. Sugimoto, T. Ta, K. Kokubun, S. Kondo, T. Itakura, H. Katagiri, Y. Ota, M. Sengoku, H. Kwon, K. Sasaki, H. Kubota, K. Suzuki, K. Kimura, and A. Sai. VLSI Technology and Circuits, page 80-81. IEEE, (2022)

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5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE.S. Kondo, H. Kubota, H. Katagiri, Y. Ota, M. Hirono, T. Ta, H. Okuni, S. Ohtsuka, Y. Ojima, T. Sugimoto and 5 other author(s). ISSCC, page 94-96. IEEE, (2020)Hardware implementation of Concurrent Periodic EFSM's.H. Katagiri, M. Kirimura, K. Yasumoto, T. Higashino, and K. Taniguchi. FORTE, volume 183 of IFIP Conference Proceedings, page 285-300. Kluwer, (2000)Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization.H. Katagiri, K. Yasumoto, A. Kitajima, T. Higashino, and K. Taniguchi. DAC, page 762-767. ACM, (2000)1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.T. Sugimoto, T. Ta, K. Kokubun, S. Kondo, T. Itakura, H. Katagiri, Y. Ota, M. Sengoku, H. Kwon, K. Sasaki and 4 other author(s). VLSI Technology and Circuits, page 80-81. IEEE, (2022)A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR.T. Ta, H. Kubota, K. Kokubun, T. Sugimoto, M. Hirono, M. Sengoku, H. Katagiri, H. Okuni, S. Kondo, S. Ohtsuka and 8 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)

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Disambiguation of "Katagiri, Hisaaki"

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1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.

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Disambiguation of "Katagiri, Hisaaki"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.

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