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Systematic design flow for dynamic data management in visual texture decoder of MPEG-4., , , , , , and . ISCAS, IEEE, (2006)VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices., , , , and . DAC, page 895-900. ACM, (2022)An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs., , , and . COINS, page 1-6. IEEE, (2022)Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information., , , , , and . ASP-DAC, page 434-439. IEEE, (2008)i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing., , , , , and . IEEE Embed. Syst. Lett., 11 (2): 50-53 (2019)Direct memory access usage optimization in network applications for reduced memory latency and energy consumption., , , , , and . J. Embed. Comput., 3 (3): 241-254 (2009)Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs., , , , , and . PARCO, volume 33 of John von Neumann Institute for Computing Series, page 769-776. Central Institute for Applied Mathematics, Jülich, Germany, (2005)Results from Running an Experiment as a Service Platform for Mobile Networks., , , , , , , , , and 1 other author(s). WiNTECH, page 9-16. ACM, (2017)Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications., , , , , and . ISCAS, page 1-5. IEEE, (2018)Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems., , , and . ICASSP, page 1549-1552. IEEE, (2020)