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FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.

, , , , and . ICICDT, page 1-4. IEEE, (2015)

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III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance., , , , , , , , , and 4 other author(s). ESSDERC, page 261-264. IEEE, (2022)Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , and . ESSDERC, page 412-415. IEEE, (2016)Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling., , , , , , , , , and 15 other author(s). ICICDT, page 145-148. IEEE, (2018)The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices., , , , , , , , , and 2 other author(s). IRPS, page 5. IEEE, (2015)ESD characterization of planar InGaAs devices., , , , , , , , , and 7 other author(s). IRPS, page 3. IEEE, (2015)A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs., , , , , , , , and . ESSDERC, page 152-155. IEEE, (2023)Silicon LEDs in FinFET technology., , , , , and . ESSDERC, page 274-277. IEEE, (2014)Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies., , , , , , , , , and 5 other author(s). ISSCC, page 528-529. IEEE, (2008)1.3 Future Scaling: Where Systems and Technology Meet.. ISSCC, page 25-29. IEEE, (2020)Impact of channel thickness scaling on the performance of GaN-on-Si RF HEMTs on highly C-doped GaN buffer., , , , , , , , , and 4 other author(s). ESSDERC, page 384-387. IEEE, (2022)