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Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Y. Zhao, Z. Lin, X. Wu, Q. Zhao, W. Lu, C. Peng, Z. Tong, and J. Chen. IEEE Trans. Very Large Scale Integr. Syst., 30 (5): 566-578 (2022)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche ChromatographieJ. Wu. Uni Erlangen-Nürnberg, (2009)

Zongmin Wu

Dagang Wu

Weijia Wu

Hongzhong Wu

Other publications of authors with the same name

Radiation-hardened 14T SRAM cell by polar design for space applications.L. Hao, B. Qiang, C. Dai, C. Peng, W. Lu, Z. Lin, L. Liu, Q. Zhao, X. Wu, and F. Sun. IEICE Electron. Express, 20 (13): 20230083 (2023)A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM.Y. Zhou, Z. Yang, Y. Wei, X. Lin, S. Wu, W. Lu, C. Peng, X. Li, and X. Wu. ISCAS, page 1-5. IEEE, (2024)SRAM-Based Digital CIM Macro for Linear Interpolation and MAC.Z. Lin, Y. Liu, Y. Wang, Y. Zhao, C. Peng, and X. Wu. ISCAS, page 1-5. IEEE, (2024)An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices.Y. Zhou, Y. Wei, T. Xiong, Z. Zhou, Z. Yang, X. Lin, W. Hu, X. Wu, and C. Peng. Microelectron. J., (2024)Design of radiation-hardened memory cell by polar design for space applications.L. Hao, L. Liu, Q. Shi, B. Qiang, Z. Li, N. Liu, C. Dai, Q. Zhao, C. Peng, W. Lu and 2 other author(s). Microelectron. J., (February 2023)Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense.Y. Zhou, X. Lin, Z. Zhou, Y. Sun, Y. Wei, Z. Yang, C. Dai, J. Zhong, X. Wu, and C. Peng. IEEE Trans. Circuits Syst. I Regul. Pap., 71 (9): 4019-4031 (September 2024)A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.S. Gao, J. Chen, D. Ke, and X. Wu. APCCAS, page 1465-1468. IEEE, (2006)14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.Z. Yuan, Y. Yang, J. Yue, R. Liu, X. Feng, Z. Lin, X. Wu, X. Li, H. Yang, and Y. Liu. ISSCC, page 232-234. IEEE, (2020)A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.Z. Lin, S. Zhang, Q. Jin, J. Xia, Y. Liu, K. Yu, J. Zheng, X. Xu, X. Fan, K. Li and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (6): 776-788 (June 2023)Threshold Switching Memristor-Based Voltage Regulative Circuit.Z. Wu, C. Zhang, J. Zou, C. Peng, and X. Wu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1034-1038 (March 2023)

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Disambiguation of "Wu, Xiulong"

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Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Please choose a person to relate this publication to

Jinglan Wu

Zongmin Wu

Dagang Wu

Weijia Wu

Hongzhong Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, Xiulong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Please choose a person to relate this publication to

Jinglan Wu

Zongmin Wu

Dagang Wu

Weijia Wu

Hongzhong Wu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.