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The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip., , , , и . Sensors, 13 (7): 8771-8785 (2013)Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing., , , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 30 (5): 566-578 (2022)Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports., , , , , , , и . IEEE J. Solid State Circuits, 56 (9): 2832-2844 (2021)Challenges and Solutions of the TFET Circuit Design., , , , , , , , , и . IEEE Trans. Circuits Syst., 67-I (12): 4918-4931 (2020)A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design., , , и . APCCAS, стр. 1465-1468. IEEE, (2006)Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments., , , , , , и . Int. J. Circuit Theory Appl., 51 (1): 398-409 (января 2023)A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination., , , , , , , , , и . IEICE Electron. Express, 15 (15): 20180604 (2018)An inverter chain with parallel output nodes for eliminating single-event transient pulse., , , , , , , , и . IEICE Electron. Express, 16 (4): 20181118 (2019)A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier., , , , , , и . IEICE Electron. Express, 12 (5): 20150102 (2015)