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Efficient variable ordering and partial representation algorithm.

, , , , , and . VLSI Design, page 81-86. IEEE Computer Society, (1995)

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Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams., , , and . DAC, page 417-420. ACM, (1991)Linear finite state machine for lD ILAs., , , and . VTS, page 325-332. IEEE Computer Society, (1994)Exact ordered binary decision diagram size when representing classes of symmetric functions., , and . J. Electron. Test., 2 (3): 243-259 (1991)Functional Approaches to Generating Orderings for Efficient Symbolic Representations., , and . DAC, page 624-627. IEEE Computer Society Press, (1992)Fast functional evaluation of candidate OBDD variable orderings., , , and . EURO-DAC, page 4-10. EEE Computer Society, (1991)Memory BIST Using ESP., , , , and . VTS, page 243-248. IEEE Computer Society, (2004)Testability of one dimensional ILAs under multiple faults., , and . VTS, page 178-181. IEEE Computer Society, (1993)Signal probability calculations using partial functional manipulation., and . VTS, page 194-200. IEEE Computer Society, (1993)Conversion of small functional test sets of nonscan blocks to scan patterns., , and . ITC, page 691-700. IEEE Computer Society, (2000)LFSR based deterministic hardware for at-speed BIST., , , and . VTS, page 201-207. IEEE Computer Society, (1993)