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Efficient variable ordering and partial representation algorithm.

, , , , , and . VLSI Design, page 81-86. IEEE Computer Society, (1995)

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Research in Reliable VLSI Architectures at the University of Illinois.. FJCC, page 890-893. IEEE Computer Society, (1986)Design of Test Pattern Generators for Built-In Test., , and . ITC, page 315-319. IEEE Computer Society, (1984)Real-time checking of linear control systems using analog checksums., , , and . IOLTS, page 122-127. IEEE, (2013)Memory Distribution: Techniques and Practice for CAD Applications., , and . Parallel Comput., 24 (11): 1597-1615 (1998)Test data compression and test time reduction using an embedded microprocessor., and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 853-862 (2003)Delay Defect Diagnosis Methodology Using Path Delay Measurements., , and . IEICE Trans. Electron., 98-C (10): 991-994 (2015)A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers., , , and . IEEE J. Solid State Circuits, 54 (8): 2140-2148 (2019)Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems., and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 785-789 (2012)Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits., and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (10): 743-747 (2014)A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages., , , and . J. Electron. Test., 19 (2): 149-160 (2003)