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Disambiguation of "Bhardwaj, Sarvesh"

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Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.

, , , and . DAC, page 791-796. ACM, (2006)

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Sarvesh Varma

Ranjit Bhardwaj

Sumit Bhardwaj

Vidhi Bhardwaj

Avinash Bhardwaj

 

Other publications of authors with the same name

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage., , and . ASP-DAC, page 953-958. IEEE, (2006)An efficient combinationality check technique for the synthesis of cyclic combinational circuits., , , , and . ASP-DAC, page 212-215. ACM Press, (2005)A framework for statistical timing analysis using non-linear delay and slew models., , and . ICCAD, page 225-230. ACM, (2006)Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic., , and . VLSI Design, page 240-. IEEE Computer Society, (2004)Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (3): 445-455 (2008)Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits., , , and . DAC, page 791-796. ACM, (2006)Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory., and . J. Low Power Electron., 4 (1): 68-80 (2008)LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs., , and . ISQED, page 717-722. IEEE Computer Society, (2006)Estimation of signal arrival times in the presence of delay noise., , and . ICCAD, page 418-422. ACM / IEEE Computer Society, (2002)Predictive Modeling of the NBTI Effect for Reliable Design., , , , and . CICC, page 189-192. IEEE, (2006)