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An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology.

, and . ISCAS, page 4257-4260. IEEE, (2010)

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Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing., and . ISCAS, IEEE, (2006)Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array., and . ECCTD, page 84-87. IEEE, (2007)A CMOS general-purpose sampled-data analogue microprocessor., and . ISCAS, page 417-420. IEEE, (2000)A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities., and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (10): 2420-2431 (2011)Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array., and . Int. J. Circuit Theory Appl., 39 (9): 963-972 (2011)Fast retinal vessel tree extraction: A pixel parallel approach., , , and . Int. J. Circuit Theory Appl., 36 (5-6): 641-651 (2008)Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing., and . J. Signal Process. Syst., 56 (1): 91-103 (2009)Architecture of asynchronous cellular processor array for image skeletonization., and . ECCTD, page 81-84. IEEE, (2005)Pixel interlacing to trade off the resolution of a cellular processor array against more registers., , , and . ECCTD, page 1-4. IEEE, (2015)A field programmable array core for image processing (abstract only)., and . FPGA, page 266. ACM, (2012)