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Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features.

, , , and . Microprocess. Microsystems, (2018)

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Parallel video processing on FPGA architecture., , , , , and . Int. J. High Perform. Syst. Archit., 8 (3): 169-178 (2018)Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation., , , , , and . CRiSIS, volume 12026 of Lecture Notes in Computer Science, page 113-127. Springer, (2019)Detecting driver drowsiness based on single electroencephalography channel., , , and . SSD, page 16-21. IEEE, (2016)Integrated temporal partitioning and partial reconfiguration techniques for design latency improvement., , and . Evol. Syst., 5 (2): 133-141 (2014)Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis., , and . IET Circuits Devices Syst., 13 (4): 534-543 (2019)Design of hardware RGB to HMMD converter based on reversible logic., and . IET Image Processing, 11 (8): 646-655 (2017)A comparison between ANN and SVM classifier for drowsiness detection based on single EEG channel., , , and . ATSIP, page 443-446. IEEE, (2016)Design of Efficient Quantum-Dot Cellular Automata (QCA) MAC Unit., , and . ICM, page 1-4. IEEE, (2018)DTR-HAR: deep temporal residual representation for human activity recognition., , , , and . Vis. Comput., 38 (3): 993-1013 (2022)Memory Efficient Deployment of an Optical Flow Algorithm on GPU Using OpenMP., , , and . ICIAP (2), volume 11752 of Lecture Notes in Computer Science, page 477-487. Springer, (2019)