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Disambiguation of "Park, Jongsun"

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A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration.

, , , , and . DAC, page 739-744. IEEE, (2021)

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Sungjune Park

Rosemary Park

Eunhong Park

Younggyu Park

Hyeyoung Park

 

Other publications of authors with the same name

Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme., , and . ISCAS, page 1-4. IEEE, (2019)A low power reconfigurable DCT architecture to trade off image quality for computational complexity., and . ICASSP (5), page 17-20. IEEE, (2004)Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers., , , and . IEEE Access, (2020)A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption., and . J. Signal Process. Syst., 53 (3): 399-410 (2008)Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 787-793 (2010)Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling., , , and . IET Circuits Devices Syst., 4 (6): 469-478 (2010)Low Power SOT-MRAM Cell Configuration For Dual Write Operation., , and . ICEIC, page 1-3. IEEE, (2021)Key Length Reconfigurable ARIA Hardware with S-box Optimization., , and . ICEIC, page 1-3. IEEE, (2021)Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance., , and . ISCAS, page 1-5. IEEE, (2021)Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit., and . ISOCC, page 147-148. IEEE, (2020)