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Disambiguation of "Hanumolu, Pavan Kumar"

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A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.

, , , , , and . ISSCC, page 392-394. IEEE, (2018)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , and . VLSIC, page 188-189. IEEE, (2012)10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS., , , , and . ISSCC, page 182-183. IEEE, (2017)A low spur fractional-N frequency synthesizer architecture., , , and . ISCAS (3), page 2807-2810. IEEE, (2005)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC., , , , and . IEEE J. Solid State Circuits, 50 (4): 867-881 (2015)A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 445-457 (2018)A 0.016 mm2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS., , and . IEEE J. Solid State Circuits, 54 (8): 2186-2194 (2019)Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers., , , and . IEEE J. Solid State Circuits, 44 (2): 427-435 (2009)A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning., , , and . IEEE J. Solid State Circuits, 41 (12): 2720-2728 (2006)