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Disambiguation of "Ikeda, Sho"

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A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET.

, , , , and . A-SSCC, page 365-368. IEEE, (2014)

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Yukihiro Ikeda

Mitsuyoshi Ikeda

Shingo Ikeda

Yoshikazu Ikeda

Wakako Ikeda-Ohtsubo

 

Other publications of authors with the same name

Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique., , , , , , , , , and 3 other author(s). ASP-DAC, page 43-44. IEEE, (2017)Optimal design method for chip-area-efficient CMOS low-dropout regulator., , , and . APCCAS, page 332-335. IEEE, (2012)An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor., , , , , and . ASP-DAC, page 23-24. IEEE, (2014)A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network., , , , , , , , , and . ASP-DAC, page 40-41. IEEE, (2015)Fused BVH to Ray Trace Level of Detail Meshes., , and . SIGGRAPH Asia Posters, page 28:1-28:2. ACM, (2022)A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS., , , , , , , and . ISOCC, page 32-35. IEEE, (2011)A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET., , , , and . A-SSCC, page 365-368. IEEE, (2014)A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna., , , , , , , , and . ISCAS, page 1218-1221. IEEE, (2015)