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Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization.

M. Vemparala, N. Fasfous, L. Frickenstein, A. Frickenstein, A. Singh, D. Salihu, C. Unger, N. Nagaraja, and W. Stechele. BMVC, page 60. BMVA Press, (2021)

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Walter Stechele

Max Stechele

Other publications of authors with the same name

Design of fine-grained sequential approximate circuits using probability-aware fault emulation.D. May, and W. Stechele. ISLPED, page 73-78. IEEE, (2015)Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems.C. Claus, R. Ahmed, F. Altenried, and W. Stechele. ARC, volume 5992 of Lecture Notes in Computer Science, page 55-67. Springer, (2010)Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources.M. Feilen, M. Ihmig, C. Schwarzbauer, and W. Stechele. FPL, page 75-82. IEEE, (2012)Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems.M. Frischke, A. Rohatschek, and W. Stechele. IOLTS, page 81-86. IEEE, (2014)Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands.N. Fasfous, M. Vemparala, A. Frickenstein, M. Badawy, F. Hundhausen, J. Höfer, N. Nagaraja, C. Unger, H. Vögel, J. Becker and 2 other author(s). ICRA, page 13430-13437. IEEE, (2021)Pruning CNNs for LiDAR-based Perception in Resource Constrained Environments.M. Vemparala, A. Singh, A. Mzid, N. Fasfous, A. Frickenstein, F. Mirus, H. Vögel, N. Nagaraja, and W. Stechele. IV Workshops, page 228-235. IEEE, (2021)Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands.S. Friedrich, S. Sampath, R. Wittig, M. Vemparala, N. Fasfous, E. Matús, W. Stechele, and G. Fettweis. ISQED, page 1-8. IEEE, (2023)WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration.P. Morì, S. Sampath, L. Frickenstein, M. Vemparala, N. Fasfous, A. Frickenstein, W. Stechele, and C. Passerone. DAC, page 1-6. IEEE, (2023)Efficient power modeling techniques for combinational and sequential RTL macroblocks.M. Eiermann, and W. Stechele. ICECS, page 705-708. IEEE, (2002)Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis.T. Mahnke, W. Stechele, M. Embacher, and W. Hoeld. ICECS, page 697-700. IEEE, (2002)

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Disambiguation of "Stechele, Walter"

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Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization.

Please choose a person to relate this publication to

Walter Stechele

Walter Stechele

Walter Stechele

Max Stechele

Max Stechele

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Stechele, Walter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization.

Please choose a person to relate this publication to

Walter Stechele

Walter Stechele

Walter Stechele

Max Stechele

Max Stechele

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization.