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A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.

S. Jeloka, P. Prabhat, G. Knight, and J. Myers. ISLPED, page 1-6. IEEE, (2019)

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Quality-of-Service for a High-Radix Switch.N. Abeyratne, S. Jeloka, Y. Kang, D. Blaauw, R. Dreslinski, R. Das, and T. Mudge. DAC, page 163:1-163:6. ACM, (2014)A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup.P. Prabhat, G. Knight, S. Jeloka, S. Yang, and J. Myers. A-SSCC, page 183-186. IEEE, (2018)System technology co-optimization and design challenges for 3D IC.S. Jeloka, B. Cline, S. Das, B. Labbe, A. Rico, R. Herberholz, J. DeLaCruz, R. Mathur, and S. Hung. CICC, page 1-6. IEEE, (2022)A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin.Q. Dong, S. Jeloka, M. Saligane, Y. Kim, M. Kawaminami, A. Harada, S. Miyoshi, M. Yasuda, D. Blaauw, and D. Sylvester. IEEE J. Solid State Circuits, 53 (4): 1006-1015 (2018)A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell.S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw. VLSIC, page 272-. IEEE, (2015)A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applications.X. Wu, Y. Shi, S. Jeloka, K. Yang, I. Lee, D. Sylvester, and D. Blaauw. VLSI Circuits, page 1-2. IEEE, (2016)Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications.S. Jeloka, Z. Wang, R. Xie, S. Khanna, S. Bartling, D. Sylvester, and D. Blaauw. VLSI Circuits, page 85-86. IEEE, (2018)A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.S. Jeloka, P. Prabhat, G. Knight, and J. Myers. ISLPED, page 1-6. IEEE, (2019)27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power.P. Prabhat, B. Labbé, G. Knight, A. Savanth, J. Svedas, M. Walker, S. Jeloka, P. Fan, F. García-Redondo, T. Achuthan and 1 other author(s). ISSCC, page 422-424. IEEE, (2020)Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.N. Pinckney, L. Shifren, B. Cline, S. Sinha, S. Jeloka, R. Dreslinski, T. Mudge, D. Sylvester, and D. Blaauw. DAC, page 76:1-76:6. ACM, (2016)

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A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.

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A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.