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Disambiguation of "Lewis, David M."

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Arria™ 10 device architecture.

, , , , , , , , , , , , , , , , , and . CICC, page 1-8. IEEE, (2015)

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J. D. Lewis-Williams

David M Eche

David M Eche

David M Stec

David M Allen

 

Other publications of authors with the same name

Algorithm design for a 30-bit integrated logarithmic processor., and . IEEE Symposium on Computer Arithmetic, page 192-199. IEEE, (1989)Swamp: A Fast Processor for Smalltalk-80., , , and . OOPSLA, page 131-139. ACM, (1986)SIGPLAN Notices 21(11).Generating highly-routable sparse crossbars for PLDs., , and . FPGA, page 155-164. ACM, (2000)Improving FPGA Performance and Area Using an Adaptive Logic Module., , , , , , , , , and 3 other author(s). FPL, volume 3203 of Lecture Notes in Computer Science, page 135-144. Springer, (2004)Synthesizing datapath circuits for FPGAs with emphasis on area minimization., , and . FPT, page 219-226. IEEE, (2002)Cyclone ™: a low-cost, high-performance FPGA., , , , , , , , , and . CICC, page 49-52. IEEE, (2003)Architecture of datapath-oriented coarse-grain logic and routing for FPGAs., , and . CICC, page 61-64. IEEE, (2003)An accurate LNS arithmetic unit using interleaved memory function interpolator.. IEEE Symposium on Computer Arithmetic, page 2-9. IEEE Computer Society/, (1993)Stratix™ 10 High Performance Routable Clock Networks., , , and . FPGA, page 64-73. ACM, (2016)Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays., and . FPGA, page 51-57. ACM, (1996)