( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Fault-Tolerant Vertical Link Design for Effective 3D Stacking.

, , , , и . IEEE Comput. Archit. Lett., 10 (2): 41-44 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

René Roca

Vincent Roca

François Rocaboy

Rodrigo Alberto Rocamora Zuñiga

Olga Antoni

 

Другие публикации лиц с тем же именем

A hierarchical approach for generating regular floorplans., , и . ICCAD, стр. 655-662. IEEE, (2014)Enabling High-Performance Crossbars through a Floorplan-Aware Design., , , , и . ICPP, стр. 269-278. IEEE Computer Society, (2012)Built-in fast gather control network for efficient support of coherence protocols., , и . IET Comput. Digit. Tech., (2013)VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks., , , и . HiPC, стр. 1-12. IEEE Computer Society, (2010)DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis., , , и . DAC, стр. 45:1-45:6. ACM, (2017)A Latency-Efficient Router Architecture for CMP Systems., , , и . DSD, стр. 165-172. IEEE Computer Society, (2010)Improved Pixel-Based Rate Allocation for Pixel-Domain Distributed Video Coders Without Feedback Channel., , , , и . ACIVS, том 4678 из Lecture Notes in Computer Science, стр. 663-674. Springer, (2007)Fault-Tolerant Vertical Link Design for Effective 3D Stacking., , , , и . IEEE Comput. Archit. Lett., 10 (2): 41-44 (2011)Reduced decoder complexity and latency in pixel-domain Wyner-Ziv video coders., , , , и . Signal Image Video Process., 2 (2): 129-140 (2008)Silicon-aware distributed switch architecture for on-chip networks., , , , и . J. Syst. Archit., 59 (7): 505-515 (2013)