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28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS., , , , , , and . ISSCC, page 470-471. IEEE, (2014)Characteristics of LNA Operation in Direct Delta-Sigma Receivers., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 70-74 (2014)N-path gmC filter modeling and analysis for direct delta-sigma receiver., , , and . NEWCAS, page 277-280. IEEE, (2012)A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 50 (3): 644-655 (2015)Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 234-243 (2015)Design tradeoffs in N-path GmC integrators for direct delta-sigma receivers., , , , , and . ECCTD, page 1-4. IEEE, (2013)Chip-to-chip communications using capacitive interconnects., and . ISCAS, page 2888-2891. IEEE, (2010)A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator., , , , , , and . ESSCIRC, page 371-374. IEEE, (2014)