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Full-Duplex Wireless Transceiver Self-Interference Cancellation Through FD-SOI Buried-Gate Signaling., , , , , , , and . ISCAS, page 1-5. IEEE, (2018)A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching., , , , , , and . ISCAS, page 1-4. IEEE, (2017)A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator., , , , , , and . ESSCIRC, page 371-374. IEEE, (2014)A Systematic Design Method for Direct Delta-Sigma Receivers., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (8): 2389-2402 (2018)A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 50 (3): 644-655 (2015)Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 234-243 (2015)Design tradeoffs in N-path GmC integrators for direct delta-sigma receivers., , , , , and . ECCTD, page 1-4. IEEE, (2013)Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup., , , , and . NORCAS, page 1-4. IEEE, (2018)A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures., , , , , , and . NORCAS, page 1-4. IEEE, (2016)Characteristics of LNA Operation in Direct Delta-Sigma Receivers., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 70-74 (2014)