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Effect of Power Optimizations on Soft Error Rate.

, , , , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 1-20. Springer, (2003)

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TaPEr: tackling power emergencies in the dark silicon era by exploiting resource scalability., , and . Conf. Computing Frontiers, page 16:1-16:8. ACM, (2015)Optimizing power and performance for reliable on-chip networks., , , , , and . ASP-DAC, page 431-436. IEEE, (2010)Numerical limitations on the design of digit online networks., and . IEEE Symposium on Computer Arithmetic, page 156-161. IEEE Computer Society, (1983)Regular, area-time efficient carry-lookahead adders., and . IEEE Symposium on Computer Arithmetic, page 9-15. IEEE, (1985)Reducing non-deterministic loads in low-power caches via early cache set resolution., , and . Microprocess. Microsystems, 31 (5): 293-301 (2007)The design and use of simplepower: a cycle-accurate energy estimation tool., , , and . DAC, page 340-345. ACM, (2000)Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint., , and . ISLPD, page 167-172. ACM, (1995)Editorial.. ACM Trans. Design Autom. Electr. Syst., 5 (3): 265-266 (2000)Exploring technology alternatives for nano-scale FPGA interconnects., , and . DAC, page 921-926. ACM, (2005)An Overview of the Penn State Design System., and . DAC, page 516-522. IEEE Computer Society Press / ACM, (1987)