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Effect of Power Optimizations on Soft Error Rate.

, , , , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 1-20. Springer, (2003)

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Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations., , , , and . ISCAS, page 1-5. IEEE, (2019)A Dual-VDD Low Power FPGA Architecture., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 145-157. Springer, (2004)A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays., , , , , and . ASP-DAC, page 118-123. IEEE, (2015)Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)., , , , and . FPGA, page 265. ACM, (2005)Ferroelectric Transistor based Non-Volatile Flip-Flop., , , , , and . ISLPED, page 10-15. ACM, (2016)Editorial., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 1 (2015)Robust Coreset Construction for Distributed Machine Learning., , , , , and . IEEE J. Sel. Areas Commun., 38 (10): 2400-2417 (2020)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility., , , , , , , , , and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Experimental Evaluation of Energy Behavior of Iteration Space Tiling., , , and . LCPC, volume 2017 of Lecture Notes in Computer Science, page 142-157. Springer, (2000)NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs., , , , , , , , and . ISCA, page 363-376. IEEE, (2020)