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Disambiguation of "Mak, Pui-In"

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A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3991-4004 (2019)

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Ellen Mak

Beatrice Puiu

Rebecca Mak

Kwok Mak

Ale PuÌ

 

Other publications of authors with the same name

An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners., , and . ISCAS, page 668-671. IEEE, (2008)A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance., , and . ISCAS, page 289-292. IEEE, (2011)26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loop., , and . ISSCC, page 452-454. IEEE, (2016)Micropower two-stage amplifier employing recycling current-buffer Miller compensation., , , , and . ISCAS, page 1889-1892. IEEE, (2014)Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With200 Million Training CRPs., , , , , and . IEEE Trans. Inf. Forensics Secur., (2023)A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (1): 51-63 (2022)Simple-Logic Comparator-Offset Mitigation Technique for Resistor-Based Temperature Sensor in DFLL., , , and . ICTA, page 1-2. IEEE, (2023)A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS., , , and . A-SSCC, page 283-284. IEEE, (2019)A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop., , and . IEEE J. Solid State Circuits, 52 (8): 2055-2070 (2017)A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays., , , , , and . IEEE J. Solid State Circuits, 52 (1): 284-297 (2017)